Table of Contents
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Table
Number
10-2
Timing Attributes Summary ................................................................................... 10-11
10-3
Programming Rules for Timing Strobes ................................................................. 10-22
10-4
Write Enable/Byte Enable Signals Function........................................................... 10-25
10-5
Memory Controller Functionality from Reset ........................................................ 10-28
10-6
Boot Bank Fields Values After Hard Reset............................................................. 10-29
10-7
Memory Controller Address Map ........................................................................... 10-33
10-8
MSTAT Bit Descriptions........................................................................................ 10-34
10-9
BR0–BR3 Bit Descriptions .................................................................................... 10-35
10-10
BRx[V] Reset Value............................................................................................... 10-36
10-11
OR0–OR3 Bit Descriptions ................................................................................... 10-37
10-12
DMBR Bit Descriptions.......................................................................................... 10-38
10-13
DMOR Bit Descriptions.......................................................................................... 10-40
11-1
DMPU Registers ....................................................................................................... 11-7
11-2
Reservation Snoop Support..................................................................................... 11-10
11-3
L2U_MCR LSHOW Modes ....................................................................................11-11
11-4
L2U Show Cycle Support Chart ............................................................................. 11-13
11-5
L2U (PPC) Register Decode ................................................................................... 11-14
11-6
Hex Address For SPR Cycles ................................................................................. 11-14
11-7
L2U_MCR Bit Descriptions .................................................................................. 11-15
11-8
L2U_RBAx Bit Descriptions ................................................................................. 11-16
11-9
L2U_RAx Bit Descriptions.................................................................................... 11-17
11-10
L2U_GRA Bit Descriptions................................................................................... 11-18
12-1
STOP and HSPEED Bit Functionality...................................................................... 12-3
12-2
Bus Cycles and System Clock Cycles....................................................................... 12-3
12-3
ILBS Signal Functionality ........................................................................................ 12-5
12-4
IRQMUX Functionality ............................................................................................ 12-6
12-5
UIMB Interface Register Map .................................................................................. 12-7
12-6
UMCR Bit Descriptions............................................................................................ 12-8
12-7
UIPEND Bit Descriptions ......................................................................................... 12-9
13-1
QADC64E A Address Map....................................................................................... 13-3
13-2
QADC64E Bus Error Response .............................................................................. 13-10
13-3
QADCINT Bit Descriptions.................................................................................... 13-11
13-4
PORTQA Bit Descriptions...................................................................................... 13-13
13-5
QACR1 Bit Descriptions ........................................................................................ 13-14
13-6
Queue 1 Operating Modes ...................................................................................... 13-15
13-7
QACR2 Bit Descriptions ........................................................................................ 13-16
13-8
Queue 2 Operating Modes ...................................................................................... 13-17
13-9
QASR0 Bit Descriptions ......................................................................................... 13-20
13-10
Pause Response ....................................................................................................... 13-23
13-11
Queue Status ........................................................................................................... 13-24
13-12
QASR1 Bit Descriptions ......................................................................................... 13-26
lvi
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Tables
Title
MPC533 Reference Manual
Page
Number
MOTOROLA
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