Motorola MPC533 Reference Manual page 60

Table
Number
17-33 MPIOSM I/O Signal Function ................................................................................ 17-61
17-34 MPIOSMDR Bit Descriptions ................................................................................ 17-63
17-35 MPIOSMDDR Bit Descriptions ............................................................................. 17-63
17-36 MIOS14SR0 Bit Description .................................................................................. 17-66
17-37 MIOS14ER0 Bit Descriptions ................................................................................ 17-67
17-38 MIOS14PR0 Bit Descriptions................................................................................. 17-67
17-39 MIOS14SR1 Bit Descriptions................................................................................. 17-68
17-40 MIOS14ER1 Bit Descriptions ................................................................................ 17-68
17-41 MIOS14PR1 Bit Descriptions................................................................................. 17-69
17-42 MBISM Interrupt Registers Address Map .............................................................. 17-70
17-43 MIOS14LVL0 Bit Descriptions .............................................................................. 17-70
17-44 MIOS14LVL1 Bit Descriptions .............................................................................. 17-71
18-1 PPM Memory Map.................................................................................................... 18-2
18-2 PPMMCR Bit Descriptions..................................................................................... 18-10
18-3 PPMPCR Bit Descriptions ...................................................................................... 18-11
18-4 SAMP[0:2] Bit Settings .......................................................................................... 18-12
18-5 PPMPCR[CM] and PPMPCR[STR] Bit Operation ................................................ 18-14
18-6 Configuration Register (TX and RX) Channel Settings ......................................... 18-16
18-7 SHORT_REG Bit Descriptions............................................................................... 18-18
18-8 SHORT_CH_REG Bit Descriptions ....................................................................... 18-20
18-9 Examples of the SHORT_CH Bits.......................................................................... 18-20
18-10 SCALE_TCLK Frequencies ................................................................................... 18-21
18-11 SCALE_TCLK_REG Bit Descriptions .................................................................. 18-21
19-1 UC3F External Interface Signals .............................................................................. 19-3
19-2 UC3F Register Programming Model ........................................................................ 19-5
19-3 UC3FMCR Bit Descriptions ..................................................................................... 19-5
19-4 UC3FMCRE Bit Descriptions .................................................................................. 19-9
19-5 UC3FCTL Bit Descriptions .................................................................................... 19-11
19-6 RCW Bit Descriptions ............................................................................................ 19-16
19-7 Program Interlock State Descriptions ..................................................................... 19-23
19-8 Erase Interlock State Descriptions .......................................................................... 19-27
19-9 Censorship States .................................................................................................... 19-30
19-10 Censorship Modes and Censorship Status .............................................................. 19-31
20-1 CRAMMCR Bit Descriptions ................................................................................... 20-8
20-2 CRAMMCR Privilege Bit Assignment for 8-Kbyte Array Blocks ........................ 20-10
20-3 CRAM_RBAx Bit Descriptions.............................................................................. 20-11
20-4 RGN_SIZE Encoding ............................................................................................. 20-11
20-5 CRAMOVLCR Bit Descriptions ............................................................................ 20-12
21-1 VF Pins Instruction Encodings ................................................................................. 21-3
21-2 VF Pins Queue Flush Encodings .............................................................................. 21-4
21-3 VFLS Pin Encodings................................................................................................. 21-4
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Tables
Title
MPC533 Reference Manual
Page
Number
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