Motorola MPC533 Reference Manual page 43

Figure
Number
15-17 CR[0:F] — Command RAM 0x30 51C0, 0x30 51DF............................................ 15-25
15-18 Flowchart of QSPI Initialization Operation ............................................................ 15-30
15-19 Flowchart of QSPI Master Operation (Part 1) ........................................................ 15-31
15-20 Flowchart of QSPI Master Operation (Part 2) ........................................................ 15-32
15-21 Flowchart of QSPI Master Operation (Part 3) ........................................................ 15-33
15-22 Flowchart of QSPI Slave Operation (Part 1) .......................................................... 15-34
15-23 Flowchart of QSPI Slave Operation (Part 2) .......................................................... 15-35
15-24 SCI Transmitter Block Diagram ............................................................................. 15-46
15-25 SCI Receiver Block Diagram.................................................................................. 15-47
15-26 SCCxR0 — SCI Control Register 0........................................................................ 15-49
15-27 SCI Control Register 1 (SCCxR1) .......................................................................... 15-50
15-28 SCIx Status Register (SCxSR) ................................................................................ 15-52
15-29 SCI Data Register (SCxDR) ................................................................................... 15-54
15-30 Start Search Example .............................................................................................. 15-61
15-31 QSCI1 Control Register (QSCI1CR) ...................................................................... 15-64
15-32 QSCI1 Status Register (QSCI1SR)......................................................................... 15-65
15-33 Queue Transmitter Block Enhancements................................................................ 15-67
15-34 Queue Transmit Flow.............................................................................................. 15-69
15-35 Queue Transmit Software Flow .............................................................................. 15-70
15-36 Queue Transmit Example for 17 Data Bytes .......................................................... 15-72
15-37 Queue Transmit Example for 25 Data Frames........................................................ 15-73
15-38 Queue Receiver Block Enhancements .................................................................... 15-74
15-39 Queue Receive Flow ............................................................................................... 15-77
15-40 Queue Receive Software Flow................................................................................ 15-78
15-41 Queue Receive Example for 17 Data Bytes............................................................ 15-79
16-1 TouCAN Block Diagram........................................................................................... 16-1
16-2 Typical CAN Network .............................................................................................. 16-3
16-3 Extended ID Message Buffer Structure .................................................................... 16-4
16-4 Standard ID Message Buffer Structure ..................................................................... 16-4
16-5 Relationship between System Clock and CAN Bit Segments .................................. 16-9
16-6 CAN Controller State Diagram............................................................................... 16-12
16-7 Interrupt Levels on IRQ with ILBS ........................................................................ 16-22
16-8 TouCAN Message Buffer Memory Map................................................................. 16-26
16-9 TouCAN Module Configuration Register (CANMCR).......................................... 16-26
16-10 TouCAN Interrupt Configuration Register (CANICR)........................................... 16-28
16-11 Control Register 0 (CANCTRL0)........................................................................... 16-29
16-12 Control Register 1 (CANCTRL1)........................................................................... 16-30
16-13 Prescaler Divide Register........................................................................................ 16-31
16-14 Control Register 2 (CANCTRL2)........................................................................... 16-32
16-15 Free Running Timer Register (TIMER).................................................................. 16-32
16-16 Receive Global Mask Register: High (RXGMSKHI), Low (RXGMSKLO) ......... 16-33
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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