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Figure
Number
19-5
Shadow Information................................................................................................ 19-15
19-6
Hard Reset Configuration Word (UC3FCFIG) ....................................................... 19-16
19-7
512-Kbyte Array Configuration.............................................................................. 19-18
19-8
Program State Diagram ........................................................................................... 19-23
19-9
Erase State Diagram................................................................................................ 19-27
19-10
Censorship States and Transitions .......................................................................... 19-34
20-1
System Block Diagram ............................................................................................. 20-2
20-2
MPC533 Memory Map with CALRAM Address Ranges ........................................ 20-2
20-3
Standby Power Supply Configuration for CALRAM Array .................................... 20-2
20-4
CALRAM Array ....................................................................................................... 20-5
20-5
CALRAM Module Overlay Map of Flash (CLPS = 1) ............................................ 20-6
20-6
CALRAM Module Configuration Register (CRAMMCR) ...................................... 20-8
20-7
CALRAM Region Base Address Register (CRAM_RBAx) .................................. 20-10
20-8
CALRAM Overlay Configuration Register (CRAM_OVLCR)............................. 20-11
20-9
CALRAM Ownership Trace Register (CRAM_OTR) ........................................... 20-12
21-1
RCPU Instruction Flow............................................................................................. 21-9
21-2
Watchpoint and Breakpoint Support in the CPU .................................................... 21-14
21-3
Partially Supported Watchpoint/Breakpoint Example ............................................ 21-19
21-4
Instruction Support General Structure .................................................................... 21-22
21-5
Load/Store Support General Structure .................................................................... 21-24
21-6
Functional Diagram of MPC533 Debug Mode Support ......................................... 21-27
21-7
Debug Mode Logic ................................................................................................. 21-29
21-8
Debug Mode Reset Configuration .......................................................................... 21-31
21-9
Asynchronous Clock Serial Communications ........................................................ 21-39
21-10
Synchronous Self Clock Serial Communication..................................................... 21-39
21-11
Enabling Clock Mode Following Reset .................................................................. 21-40
21-12
Download Procedure Code Example ...................................................................... 21-45
21-13
Slow Download Procedure Loop ............................................................................ 21-45
21-14
Fast Download Procedure Loop.............................................................................. 21-45
21-15
Comparator A–D Value Register (CMPA–CMPD) ................................................ 21-48
21-16
Exception Cause Register (ECR) ............................................................................ 21-49
21-17
Debug Enable Register (DER) ................................................................................ 21-51
21-18
Breakpoint Counter A Value and Control Register (COUNTA)............................ 21-53
21-19
Breakpoint Counter B Value and Control Register (COUNTB)............................. 21-53
21-20
Comparator E–F Value Registers (CMPE–CMPF)................................................. 21-54
21-21
Comparator G–H Value Registers (CMPG–CMPH) .............................................. 21-54
21-22
L-Bus Support Control Register 1 (LCTRL) .......................................................... 21-55
21-23
L-Bus Support Control Register 2 (LCTRL2) ........................................................ 21-56
21-24
I-Bus Support Control Register (ICTRL) ............................................................... 21-58
21-25
Breakpoint Address Register (BAR)....................................................................... 21-61
21-26
Development Port Data Register (DPDR) .............................................................. 21-61
xlvi
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Figures
Title
MPC533 Reference Manual
Page
Number
MOTOROLA
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