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Figure
Number
10-4
Bank Base Address and Match Structure.................................................................. 10-4
10-5
A 4-2-2-2 Burst Read Cycle (One Wait State Between Bursts)................................ 10-9
10-6
4 Beat Burst Read with Short Setup Time (Zero Wait State).................................. 10-10
10-7
GPCM–Memory Devices Interface ........................................................................ 10-12
10-8
Memory Devices Interface Basic Timing (ACS = 00, TRLX = 0)......................... 10-13
10-9
Peripheral Devices Interface ................................................................................... 10-13
10-10
Peripheral Devices Basic Timing (ACS = 11, TRLX = 0)...................................... 10-14
10-11
Relaxed Timing — Read Access (ACS = 11, SCY = 1, TRLX = 1) ...................... 10-15
10-12
Relaxed Timing — Write Access
(ACS = 10, SCY = 0, CSNT = 0, TRLX = 1) .................................................... 10-16
10-13
Relaxed Timing — Write Access
(ACS = 11, SCY = 0, CSNT = 1, TRLX = 1) .................................................... 10-17
10-14
Relaxed Timing — Write Access
(ACS = 00, SCY = 0, CSNT = 1, TRLX = 1 ..................................................... 10-18
10-15
Consecutive Accesses (Write After Read, EHTR = 0) ........................................... 10-19
10-16
Consecutive Accesses (Write After Read, EHTR = 1) ........................................... 10-20
10-17
Consecutive Accesses
(Read After Read From Different Banks, EHTR = 1) ....................................... 10-21
10-18
Consecutive Accesses (Read After Read From Same Bank, EHTR = 1) ............... 10-22
10-19
Aliasing Phenomenon Illustration........................................................................... 10-26
10-20
Synchronous External Master
Configuration For GPCM-Handled Memory Devices ....................................... 10-31
10-21
Synchronous External Master Basic Access (GPCM Controlled).......................... 10-32
10-22
Memory Controller Status Register (MSTAT)........................................................ 10-34
10-23
Memory Controller Base Registers 0–3 (BR0–BR3) ............................................. 10-34
10-24
Memory Controller Option Registers 1–3 (OR0–OR3).......................................... 10-36
10-25
Dual-Mapping Base Register (DMBR)................................................................... 10-38
10-26
Dual-Mapping Option Register (DMOR) ............................................................... 10-39
11-1
L2U Bus Interface Block Diagram ........................................................................... 11-3
11-2
DMPU Basic Functional Diagram ............................................................................ 11-5
11-3
Region Base Address Example ................................................................................. 11-8
11-4
— L2U Module Configuration Register (L2U_MCR) ........................................... 11-15
11-5
L2U Region x Base Address Register (L2U_RBAx) ............................................. 11-16
11-6
L2U Region X Attribute Register (L2U_RAx)....................................................... 11-16
11-7
L2U Global Region Attribute Register (L2U_GRA).............................................. 11-17
12-1
UIMB Interface Module Block Diagram .................................................................. 12-2
12-2
IMB Clock – Full-Speed IMB Bus ........................................................................... 12-3
12-3
IMB Clock – Half-Speed IMB Bus........................................................................... 12-3
12-4
Interrupt Synchronizer Signal Flow .......................................................................... 12-4
12-5
Time-Multiplexing Protocol for IRQ Signals ........................................................... 12-5
12-6
Interrupt Synchronizer Block Diagram..................................................................... 12-7
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Figures
Title
Figures
Page
Number
xxxix
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