Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2182

symmetrical. For example, IEEE 802.3 full-duplex links include the maintenance of synchronized time during
normal operation followed by addition, removal, or failure of network components and network reconfigura-
tion.
As shown in the Transmit and Receive Path Block Diagram figure, one SCB master interface connects to three
DMA channels (channel 0, channel 1, and channel 2). The DMA arbiter helps in arbitration of all the paths (trans-
mit and receive) in channel 0, channel 1 and channel 2. Each channel has a separate control and status register
(CSR) for managing the transmit and receive functions, descriptor handling, and interrupt handling.
Figure 31-19: Transmit and Receive Path Block Diagram
Transmit Path Functions
The transmit path of channel 0 supports strict-priority algorithm and is used for best-effort traffic. For a channel,
the strict-priority algorithm determines that a frame is available for transmission if the channel contains one or more
frames. When the threshold mode for EMAC MFL Tx FIFO is enabled, the strict-priority algorithm determines
that a frame is available for transmission. The algorithm determines when the channel contains a partial frame of
size equal to the programmed threshold limit.
The transmit paths of channel 1 and channel 2 support traffic management by using the credit-based shaper algo-
rithm. For a channel, the credit-based shaper algorithm determines that a frame is available for transmission if the
following conditions are true:
• The channel contains one or more frames.
• The credit for the channel is positive as per the algorithm.
Programs can disable the credit-based shaper algorithm for all channels or for lower-priority channels. The credit-
based shaper algorithm can be disabled for channel 1 and channel 2 or for channel 1 only. When the credit-based
shaper algorithm for a channel is disabled, the channel uses the default strict-priority algorithm.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
CHANNEL 0
Tx/Rx DMA
DMA CONTROL
STATUS REGISTER
CHANNEL 1
SCB
MASTER
Tx/Rx DMA
INTERFACE
DMA CONTROL
STATUS REGISTER
CHANNEL 2
Tx/Rx DMA
DMA CONTROL
STATUS REGISTER
SCB (MMR) SLAVE INTERFACE
CHANNEL 0
Tx/Rx FIFO
TRAFFIC
MANAGEMENT
AND
SCHEDULING
(TMS FOR Rx)
CHANNEL 1
Tx/Rx FIFO
DE-MULTIPLEXING
CHANNEL 2
FOR Rx
Tx/Rx FIFO
AV FEATURE
MODULE
Audio Video Data Transmission
TIME
SYNCHRONIZATION
MAC CONTROL
STATUS REGISTERS
AV FEATURE
REGISTERS
31–91