Dma Stream X Peripheral Address Register (Dma_Sxpar) (X = 0; Dma Stream X Memory 0 Address Register (Dma_Sxm0Ar) (X = 0 - ST STM32F446 Series Reference Manual

RM0390
9.5.7

DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)

Address offset: 0x18 + 0x18 * stream number
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 PAR[31:0]: peripheral address
9.5.8 DMA stream x memory 0 address register
(DMA_SxM0AR) (x = 0..7)
Address offset: 0x1C + 0x18 * stream number
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 M0A[31:0]: memory 0 address
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Base address of the peripheral data register from/to which the data is read/written.
These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR
register.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Base address of memory area 0 from/to which the data is read/written.
These bits are write-protected. They can be written only if:
– the stream is disabled (bit EN= '0' in the DMA_SxCR register) or
– the stream is enabled (EN='1' in DMA_SxCR register) and bit CT = '1' in the
DMA_SxCR register (in double-buffer mode).
Direct memory access controller (DMA)
24 23 22
PAR[31:16]
rw rw rw
8 7 6
PAR[15:0]
rw rw rw
24 23 22
M0A[31:16]
rw rw rw
8 7 6
M0A[15:0]
rw rw rw
RM0390 Rev 4
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw
231/1328
237