Rcc Ahb3 Peripheral Clock Enable Register (Rcc_Ahb3Enr) - ST STM32WL5 Series Reference Manual

Reset and clock control (RCC)
7.4.17

RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)

Address offset: 0x050
Reset value: 0x0208 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access from
CPU1 is not supported.
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 FLASHEN: CPU1 Flash memory interface clock enable
Bits 24:21 Reserved, must be kept at reset value.
Bit 20 IPCCEN: CPU1 IPCC interface clock enable
Bit 19 HSEMEN: CPU1 HSEM clock enable
Bit 18 RNGEN: CPU1 true RNG clocks enable
Bit 17 AESEN: CPU1 AES accelerator clock enable
Bit 16 PKAEN: CPU1 PKA accelerator clock enable
Bits 15:0 Reserved, must be kept at reset value.
320/1461
28 27 26 25
FLASH
Res. Res. Res.
EN
rw
12 11 10 9
Res. Res. Res. Res.
This bit can only be cleared when the Flash memory is in power down. Set and cleared by
software.
0: Flash interface clock disabled for CPU1
1: Flash interface clock enabled for CPU1
This bit is set and cleared by software.
0: IPCC clock disabled for CPU1
1: IPCC clock enabled for CPU1
This bit is set and cleared by software.
0: HSEM clock disabled for CPU1
1: HSEM clock enabled for CPU1
This bit is set and cleared by software.
0: True RNG bus and kernel clocks disabled for CPU1
1: True RNG bus and kernel clocks enabled for CPU1
This bit is set and cleared by software.
0: AES clock disabled for CPU1
1: AES clock enabled for CPU1
This bit is set and cleared by software.
PKA clock is enabled when a hardware PKA SRAM erase is ongoing.
0: PKA clock disabled for CPU1
1: PKA clock enabled for CPU1
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0453 Rev 1
21 20 19 18
IPCC HSEM RNG
Res.
EN EN EN
rw rw rw
5 4 3 2
Res. Res. Res. Res.
RM0453
17 16
AES PKA
EN EN
rw rw
1 0
Res. Res.