Digital Bi-Directional Signals - Bayer HealthCare RapidPoint 400 Series Service Manual

Output Signal
CLK
DACK0- to DACK3-
DACK5- to DACK7-
RESETDRV
OSC
SMEMR-
SMEMW-
T/C

Digital Bi-directional Signals

Bi-directional
Signals
IOR-
IOW-
LA17-LA23
MEMR-
MEMW-
REFRESH-
Rev. C
Description
8-MHz system clock.
Used to acknowledge DMA requests. These signals are
active low.
Resets or initializes system logic at power up or during a low
voltage condition. This signal is active high.
Oscillator. This signal is a high speed clock with a 70-nS
period (14.31818 MHz) and is not synchronous with the
system clock. It has a 50% duty cycle.
Instructs the memory devices to drive data onto the data bus.
SMEMR- is active only when the memory decode is within
the low 1M of memory space. SMEMR- is derived from
MEMR- and the decode of the low 1 MB of memory. This
signal is active low.
Instructs the memory devices to store the data present on the
data bus. SMEMW- is active only when the memory decode
is within the low 1 MB of the memory space. SMEMW-
originates from MEMW- and the decode of the low 1 MB
memory. This signal is active low.
Terminal count. This signal provides a high pulse when the
terminal count for any DMA channel is reached.
Description
I/O Read signal. This signal instructs an I/O device to drive
its data onto the data bus. The system microprocessor or
DMA controller, or a microprocessor or DMA controller
resident on the I/O channel, drives the signal. This channel
is active low.
I/O Write signal. This signal instructs an I/O device to read
the data from the data bus.
Unlatched signals address memory and I/O devices.
Instructs the memory devices to drive data onto the data bus.
Instructs the memory devices to store the present data onto
the data bus.
Indicates a refresh cycle. This signal is driven by a
microprocessor on the I/O channel and is active low.
Electronic System Overview 93
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