Figure 3.4.3 Example Of Multiple Interrupts - Fujitsu F2MC-8L MB89620 Series Hardware Manual

3.4 Interrupts
3.4.3 Multiple Interrupts
Multiple interrupts can be performed by setting different interrupt levels to the
interrupt level setting register for two or more interrupt requests from peripheral
functions.
n Multiple Interrupts
If the interrupt request having the higher interrupt levels occurs during the interrupt processing
routines, the CPU halts the current interrupt process and switches to accept the interrupt with
the higher priority. Interrupt levels can be set in the range 1 to 3. However, the CPU does not
accept interrupt requests set to interrupt level 3.
Example of Multiple Interrupts
l
As an example of multiple interrupt processing, assume that an external interrupt has a higher
priority than the timer interrupt. The timer interrupt is set to level 2 and the external interrupt is
set to level 1. Figure 3.4.3 shows the processing when the external interrupt occurs during
execution of timer interrupt processing.
Initialize peripheral
Timer interrupt occurs
Restart main program
• During execution of timer interrupt processing, the interrupt level bits in the condition code
register (CCR: IL1, IL0) are automatically set to the same value as the interrupt level setting
register (ILR1, ILR2, ILR3) corresponding to the timer interrupt (level 2 in this example). If
the interrupt request set to higher interrupt level (level 1 in this example) occurs at this time,
the interrupt processing has priority.
• To temporarily disable multiple interrupts during the timer interrupt, the interrupt enable flag
in the condition code register is set to "interrupts disabled" (CCR: I = "0") or the interrupt level
bits (IL1, IL0) set to "00".
• On execution of the interrupt return instruction (RETI) at the completion of interrupt
processing, the CPU restores the program counter (PC) and program status (PS) values
saved on the stack and resumes execution of the interrupted program.
Restoring the program status (PS) returns the condition code register (CCR) to the value
prior to the interrupt.
48
CHAPTER 3 CPU
Main program Timer interrupt processing
Interrupt level 2
(CCR:IL1, IL0 = "10")
(1)
(2)
(8)

Figure 3.4.3 Example of Multiple Interrupts

Interrupt level 1
(CCR:IL1, IL0 = "01")
(3)
External interrupt
occurs
Halt
Restart
Timer interrupt
(6)
processing
(7)
Timer interrupt returns
External interrupt processing
(4) External interrupt
processing
(5)
External interrupt
returns
MB89620 series