Clk Synchronous Mode; Figure 12.4.4A Transfer Data Format (Mode 2) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

12.4.4 CLK synchronous mode

(1) Transfer data format
UART handles NRX (non return to zero) format data only. Figure 12.4.4a shows the
transmission/reception clock and data.
SODR write
RXE, TXE
SIN0, SOT0
When the internal clock (dedicated baud rate generator or internal timer) is selected, a data reception
synchronization clock is automatically generated upon data transmission.
When an external clock is selected, it is necessary to supply precisely one byte of clock after it is
confirmed that the transmission data buffer (SODR register) of the transmission UART contains data (the
TDRE flag is '0'). Ensure that the signal is at the mark level before and after transmission.
Only 8-bit data can be handled, and no parity bit can be added. Since there is no start or stop bits, no
errors are detected except for an overrun error.
(2) Initialization
The control register values for CLK synchronous mode are listed below.
SMR register
MD1 and MD0
CS2, CS1, and CS0: Clock input
SCKE
SOE
SCR register
PEN
P, SBL, A/D
CL
REC
RXE and TXE
SSR register
RIE
TIE
MB90580 Series
SCLK
1
LSB
01001101 is transferred.
B

Figure 12.4.4a Transfer data format (mode 2)

: 10
: Dedicated baud rate generator or internal timer: 1External clock: 0
: Transmission and reception: 1 Reception only: 0
: 0
: Invalid
: 1
: 0 (To be initialized)
: 1 written to one or both
: Interrupts are enabled: 1 Interrupts are disabled: 0
: 0
0 1 1 0 0 1
12.4 Operations
Mark
0
(Mode 2)
MSB
Chapter 12: UART 135