A/D Data Register (Adcr1/Adcr0) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 19 8/10-BIT A/D CONVERTER
19.3.4

A/D Data Register (ADCR1/ADCR0)

The A/D data register (ADCR1/ADCR0) stores the A/D conversion result and also has a
function to select the A/D conversion resolution.
A/D Data Register (ADCR1/ADCR0)
Address bi t15 bi t14 bi t13 bit12 bi t11 bi t10 bi t9
000043 /
H
S10 ST1 ST0 CT1 CT0
000042
H
W W
440
Figure 19.3-5 A/D Data Register (ADCR1/ADCR0)
D9
W W W R
bi t8 bi t7 bi t6 bi t5 bi t4
D8 D7 D6 D5 D4
R R R R R
D0 to D9
Conversion data
CT1 CT0
0 0 44 Machine cycle (1.83ms@24MHz)
0 1
66 Machine cycle (2.75ms@24MHz)
1 0
88 Machine cycle (3.67ms@24MHz)
1 1
176 Machine cycle (7.33ms@24MHz)
128 Machine cycle (5.33ms@24MHz)
ST1 ST0
0 0 20 Machine cycle (3.33ms@6MHz)
32 Machine cycle (5.33ms@6MHz)
0 1
1 0 48 Machine cycle (4.0ms@12MHz)
128 Machine cycle (5.33ms@24MHz)
1 1
S10
0 10-bit conversion resolution mode (D9 to D0)
1 8-bit conversion resolution mode (D7 to D0)
bit3 bi t2 bit1 bit0 Initial value
D3 D2 D1 D0
00101XXX
R R R R
XXXXXXXX
A/D data bit
Compare time setting bit
Smapling time setting bit
AD data bit
B
B