Precaution Of Using Dtp/External Interrupt - Fujitsu F2MC-16LX Hardware Manual
16-bit microcontroller mb90330 series
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- Hardware manual (598 pages) ,
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18.4
Precaution of Using DTP/External Interrupt
Notes DTP/an external interruption is used are explained.
Condition of Peripheral Equipment Connected Outside
The external peripheral device that the DTP can support must automatically clear the request at the transfer
execution. In addition, if the transfer request is not canceled within three-machine-cycle (an interim value)
after the transfer operation started, this resource handles it as if the next transfer request occurs.
Operation Process of DTP/External Interrupt
Set the registers within the DTP/external interrupt by using the following procedures:
1. Set the general purpose I/O port that is shared with the external interrupt as input port.
2. Disable the bits for the enable register.
3. The target bit for request level set register is set.
4. The target bit for the factor register is cleared.
5. Enable the bits for the enable register.
Simultaneous writing is possible for 4 and 5 with the word specification.
Before setting registers in this resource, the enable register must be disabled. In addition, before enabling
the enable register, the factor register must be cleared. These actions prevent erroneous interrupt factor
occurrence at register setting or in the interrupt enable state.
External Interrupt Request Level
• Minimum 3 machine cycles are necessary for the pulse width to detect the edge presence when the
request level is set to the edge request.
• When the request input level is set to the level setting, the request to the interrupt controller remains
active even if an external request is input and canceled afterward, in case of the interrupt request enable
state (ENIR:EN=1). To cancel the request for the interrupt controller, the interrupt request flag bit
(EIRR: ER) must be cleared.
Figure 18.4-1 Clearness of Interrupt Request Flag Bit (EIRR: ER) when Level is Set
Interrupt factor
Interrupt request
Level detection
fiag bit (EIRR: ER)
Continue to retain the factor
as long as it is not cleared.
CHAPTER 18 DTP/EXTERNAL INTERRUPT
Enable gate
to Interrupt
controller
427
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