Shift Clock Mode - Fujitsu F2MC-16LX Hardware Manual

20.3.1

Shift Clock Mode

Shift clock includes two types of modes; one is Internal Shift Clock Mode, the other is
External Shift Clock Mode, both of which are specified by settings of SMCS. Please
switch the mode with serial I/O stopped. Reading BUSY bit allows the checking of the
state of HALT.
Internal Shift Clock Mode
Operation is driven by the internal clock, and the shift clock whose duty ratio is 50% is output from SCK
pin as an output of the timing of synchronization.
Data is forwarded by one bit per a clock.
Transfer rate can be calculated using the following formula.
A indicates the rate of division represented by SMD bit of SMCS.
(φ/div)/2, (φ/div)/2
External Shift Clock Mode
In synchronization with the external shift clock input through SCK pin, 1 bit of data is transferred for each
individual clock.
Allowed transfer rate varies from DC to 1/(8 machine cycles). When 1 machine cycle = 62.5 ns for
example, a maximum of 2 MHz is allowable.
Transfer by instruction by instruction can be accomplished by setting as described below.
• Select the external shift clock mode, and set SCOE bit of SMCS to "0".
• Write "1" in the direction register of which the port shares SCK pin, and place the port in the output
mode.
Once the settings complete as indicated above, write "1" or "0" in the data register (PDR) of the port, then
the value to be delivered to SCK pin is captured as the external clock and transfer operation is
accomplished. Have the shift clock start at "H".
Note:
Writing to SMCS.SDR during serial I/O operation is disabled.
=
transfer rate (S)
Internal clock machine cycle (A)
2 4 5
, (φ/div)/2 , (φ/div)/2 , (φ/div)/2
CHAPTER 20 EXTENDED I/O SERIAL INTERFACE
A
6
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