Fujitsu F2MC-16LX Hardware Manual page 425

[bit 4] PIE0: ppg Interrupt Enable (interrupt to PPG0/PPG2/PPG4 enabled)
PPG0/PPG2/PPG4 interrupt inhibition and permission are controlled.
PIE0
0 Disables the interrupt
1 Interruption permission
• If PUF0 is changed to "1" while this bit is "1", an interrupt request is generated. If this bit is "0", no
interrupts are generated.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[bit 3] PUF0: ppg Underflow Flag (PPG0/PPG2/PPG4 counter underflow)
Detected result of counter underflow of the PPG0/PPG2/PPG4 is shown.
PUF0
0 The PPG counter underflow is not detected.
1 The PPG counter underflow was detected.
In the 8-bit PPG6 channel mode (PPG0, PPG1/PPG2, PPG3/PPG4, PPG5) and the 8-bit prescaler + 8-bit
PPG mode, the counter values of ch0, ch2, ch4 are set to "1" when they underflow from 00
16-bit PPG3 channel mode (PPG0, PPG1/PPG2, PPG3/PPG4, PPG5), the counter values of ch1, ch3, ch5/
ch0, ch2, ch4 are set to "1" when they underflow from 0000
writing in the PUF0 bit is not significant. "1" is read with a read-modify-write instruction.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[bit 2, bit 1] Undefinition bit
The read value is irregular. Nothing is affected when it is written.
[bit 0] Reserved bit
It is Reserved bit. Always set this bit to "1".
CHAPTER 17 8/16-BIT PPG TIMER
Operating State
Operating State
to FFFF . Becomes "0" by written "0". "1"
H H
to FF . In the
H H
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