Ep1 To Ep5 Status Register (Ep1S To Ep5S) - Fujitsu F2MC-16LX Hardware Manual

13.3.9

EP1 to EP5 Status Register (EP1S to EP5S)

The EP1 to EP5 status registers (EP1S to EP5S) displays status related to EndPoint1 to
EndPoint5.
EP1 to EP5 Status Register (EP1S to EP5S)
Figure 13.3-11 shows the bit configurations of the EP1 to EP5 status registers (EP1S to EP5S).
Figure 13.3-11 EP1 to EP5 Status Register (EP1S to EP5S)
Address bit 7
EP1S 0000E6
H
X
X
R/W
7
Address bit
EP2S 0000E8 Reserved
H
EP3S 0000EA
H
-
EP4S 0000EC
H
-
EP5S 0000EE
H
-
15
Address bit
EP1S 0000E7 BFINI
H
1
1
R/W
15
Address bit
EP2S 0000E9 BFINI
H
EP3S 0000EB
H
1
EP4S 0000ED
H
1
EP5S 0000EF
H
R/W
The function of each bit in the EP1 to EP5 status register (EP1S to EP5S) is described in the following.
6 5 4
X X X
X X X
R/W R/W R/W
6 5 4
X X X
X X X
R/W R/W R/W
14 13 12
DRQIE SPKIE Reserved
0 0 -
Irrelevance Irrelevance -
R/W R/W -
14 13 12
DRQIE SPKIE Reserved
0 0 -
Irrelevance Irrelevance -
R/W R/W -
3 2
SIZE
X X
X X
R/W R/W
3 2
SIZE
X X
X X
R/W R/W
11 10
BUSY DRQ
0 0
Irrelevance 0
R R/W
11 10
BUSY DRQ
0 0
Irrelevance 0
R R/W
CHAPTER 13 USB FUNCTION
1 0
←
X X
Initial value
←
X X
BFINI Reset
←
R/W R/W
Access
1 0
←
X X
Initial value
←
X X
BFINI Reset
←
R/W R/W
Access
9 8
SPK SIZE
←
0 X
Initial value
←
0 X
BFINI Reset
←
R/W R/W
Access
9 8
SPK Reserved
←
0 -
Initial value
←
0 -
BFINI Reset
←
R/W -
Access
291