Fujitsu F2MC-16LX Hardware Manual page 144

CHAPTER 5 CLOCK
Clock generation unit
X0A
Pin
Subclock
generation
X1A
circuit
Pin
X0
System
Pin
clock
X1
generation
Pin
circuit
: Oscillation clock
HCLK
MCLK : Main clock
: Sub clock
SCLK
: PLL clock
PCLK
φ
: Machine clock
128
Figure 5.1-1 Clock Supply Map
Watch timer
Timebase timer
1 2
PLL frequency
multiplication circuit
PCLK
4 division
SCLK
Clock selector
2 division
HCLK
MCLK
Peripheral function
4
Watchdog timer
4
16 - bit
PPG timer
0/1/2/3/4/5
16 - bit
PWC timer
8 - bit
4 expanded serial I/O
UART0/1/2/3
φ
16 - bit
reload timer
0/1/2
CPU
µ DMAC
External interrupt
16 - bit
output compare
0/1/2/3
16 - bit
free - run timer
16 - bit
input capture
0/1/2/3
8/10 - bit
A/D converter
USB function
USB Mini - HOST
2
I C interface
3 Oscillation stabilization
wait time
Pin
PPG0 to PPG5
Pin PWC
Pin SCK
Pin SIN
Pin
SOT
Pin
SCK0 to SCK3
Pin
SIN0 to SIN3
Pin SOT0 to SOT3
Pin
TIN0 to TIN2
Pin
TOT0 to TOT2
Pin INT0 to INT7
Pin
OUT0 to OUT3
Pin
FRCK
Pin
IN0 to IN3
Pin AN0 to 15
Pin
ADTG
Pin
DVP
Pin
DVM
Pin
HCON
Pin
VBUS
Pin
HVP
HVM
Pin
Pin
SCL0 to SCL2
Pin
SDA0 to SDA2