Fujitsu F2MC-16LX Hardware Manual page 265

Output Compare Control Registers (OCS0 to OCS3)
Figure 12.2-12 shows the bit configurations of the output compare control registers (OCS0 to OCS3).
Figure 12.2-12 Bit Configurations of Output Compare Control Registers (OCS0 to OCS3)
ch1:000055
ch3:000057
ch0:000054
ch2:000056
The function of each bit in the output compare control registers (OCS0 to OCS3) is described in the
following.
[bit 15 to bit 13] undefinition bit
The reading value is irregular. No effect on writing.
[bit 12] CMOD (Output level inverse mode bit)
If pin output is enabled (OTE1=1 or OTE0=1), pin output level inverse operation mode is switched
when there is a comparing match.
• When CMOD=0 (initial value), the pin output level that correspond to the compare register is reversed.
- OUT0/OUT2: Reverses the level at a match with the compare register 0/2.
- OUT1/OUT3: Reverses the level at a match with the compare register 1/3.
• When CMOD=1, compare register 0 reverses the output level the same way as when CMOD=0, and the
output level of the pin (OUT1) that corresponds to compare register 1 is reversed when there are
comparing matches with both compare register 0 and compare register 1. If compare register 0 and
compare register 1 have the same value, the operation would be the same as if they were one compare
register.
- OUT0/OUT2: Reverses the level at a match with the compare register 0/2.
- OUT1/OUT3: Reverses the level at a match with the compare register 1/3 and 1.
[bit 11, bit 10] OTE1,OTE0 (Output enable bit)
Bit to enable the pin output of the output compare. The initial value is "0".
0
1
• OTE1: Corresponding to output compare 1/3
• OTE0: Corresponding to output compare 0/2
15 14 13
H
H
- - -
7 6 5
H
ICP1 ICP0 ICE1 ICE0
H
R/W R/W R/W
It operates as a general-purpose port. [Initial value]
Becomes the output compare pin output.
12 11 10 9
CMOD OTE1 OTE0 OTD1 OTD0
R/W R/W R/W R/W
4 3 2 1
CST1 CST0
- -
R/W R/W
CHAPTER 12 16-BIT I/O TIMER
OCS1/OCS3
8 Output compare
control register upper
R/W Initial value
---00000
OCS0/OCS2
0 Output compare
control register lower
0000--00
Initial value
R/W
B
B
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