Fujitsu F2MC-16LX Hardware Manual page 523

Transmission Operation
• Sending data is written in the serial output data registers 0 to 3 (SODR0 to SODR3) in the state of "1"
being set to the sending data empty flag bit (SSR0 to SSR3: TDRE).
• When the sending data is written, and the bit of the serial control register indicating that sending
operation is enabled (SCR0 to SCR3: TXE) is set to "1", then sending starts.
• When the sending data is written to the serial output data register, the sending data empty flag bit (SSR0
to SSR3: TDRE) is once cleared to "0".
• When the sending data is transferred from the serial output data registers 0 to 3 (SODR0 to SODR3) to
the sending shift register, the sending data empty flag bit (SSR0 to SSR3: TDRE) is set to "1" again.
• When the sending data is transferred from the serial output data registers 0 to 3 (SODR0 to SODR3) to
the sending shift register, the sending data empty flag bit (SSR0 to SSR3: TDRE) is set to "1" again.
• When the bit indicating that the sending interrupts (SSR0 to SSR3: TIE) is enabled has already been set to
"1", a sending interrupt request is generated if the sending data empty flag bit (SSR0 to SSR3: TDRE) is
set to "1".In interrupt processing, the following data can be written to the serial output data registers 0 to
3 (SODR0 to SODR3).
Reception Operation
• Receiving operation are always performed when the receiving operations are set to be enabled (SCR0 to
SCR3: RXE=1).
• When the start bit of the receiving data is detected, one frame of data is received in the serial input data
registers 0 to 3 (SIDR0 to SIDR3) based on the data format that is set in the serial input control register 0
to 3 (SCR0 to SCR3).
• One frame of data reception is completed, the receiving data full flag bit (SSR0 to SSR3: RDRF) is set to
"1".
• When reading receiving data, check the state of error flags of the serial status registers 0 to 3 (SSR0 to
SSR3). If receiving is successful, then read the receiving data from the serial input data register. When a
reception error occurs, perform error handling.
• When the receiving data has been read, the receiving data full flag bit (SSR0 to SSR3: RDRF) is cleared
to "0".
Stop Bit
One bit or two bits length can be selected. However, the receive side always detects only the first bit.
Error detection
In mode 0, parity, overrun, and framing error can be detected.
In the operation mode 1, overrun and framing errors can be detected. But parity errors cannot be detected.
Parity bit
The addition of a parity bit can be set only in operation mode 0. The parity addition enable bit (SCR0 to
SCR3: PEN) and parity select bit (SCR0 to SCR3:P) can be used to select whether to use parity and to set
the even or odd parity, respectively.
In the operation mode 1 and 2, parity cannot be appended.
Figure 21.7-2 shows the sending and receiving data when parity bits are valid.
CHAPTER 21 UART
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