I 2 C Bus Control Register 0 (Ibcr0N) - Fujitsu MB95630H Series Hardware Manual

2
CHAPTER 24 I C BUS INTERFACE
24.7 Registers
2
24.7.1 I C Bus Control Register 0 (IBCR0n)
2
The I C bus control register 0 (IBCR0n) controls the address acknowledge in
the transmission of the first byte, selects the timing of the transfer completion
interrupt, and enables or disables the arbitration lost interrupt, the STOP
condition detection interrupt and MCU standby wakeup function.
■ Register Configuration
bit 7
Field AACKX
Attribute R/W
Initial value 0
■ Register Functions
[bit7] AACKX: Address acknowledge disable bit
This bit controls the address acknowledge in the transmission of the first byte.
Writing "0" to this bit causes the address acknowledge to be output automatically (The address acknowledge
is returned automatically if the slave address matches).
Writing "1" to this bit prevents the address acknowledge from being output.
Modify the setting of this bit in either of the following ways:
• Write "1" to this bit in master mode.
• Clear this bit to "0" after checking that the bus busy bit (IBSRn:BB) is "0".
Notes:
• If AACKX =1 and IBSRn:FBT =0 when a transfer completion interrupt is generated (IBCR1n:INT = 1), no
address acknowledge is output even though the I
bit to "0" as an interrupt is generated upon completion of transfer of each byte of address/data in the same
way as during addressing.
• If AACKX =1 and IBSRn:FBT =1 when a transfer completion interrupt is generated (IBCR1n:INT = 1), "1"
might be written to AACKX after addressing as in slave mode. Either continue normal communication after
setting AACKX to "0" again or restart communication after disabling I
bit7
Writing "0"
Writing "1"
[bit6] INTS: Timing select bit for transfer completion flag bit at data reception
This bit selects the timing of the transfer completion interrupt (IBCR1n:INT) when data is received. Modify
this bit only when IBSRn:TRX = 0 and IBSRn:FBT = 0.
Writing "0" to this bit sets the transfer completion interrupt request flag bit (IBCR1n:INT) to "1" in the ninth
SCLn cycle.
Writing "1" to this bit sets the transfer completion interrupt request flag bit (IBCR1n:INT) to "1" in the
eighth SCLn cycle.
Notes:
• The transfer completion interrupt request flag bit (IBCR1n:INT) is set to "1" always in the ninth SCLn cycle
except during data reception (IBSRn:TRX = 1 or IBSRn:FBT = 1).
• If the data acknowledge depends on the content of the received data (such as packet error checking used by
the SM bus), control the data acknowledge by setting the data acknowledge enable bit (IBCR1n:DACKE)
after writing "1" to this bit (for example, using a previous transfer completion interrupt) to read latest received
data.
514
6 5
INTS ALF
R/W R/W
0 0
Enable address acknowledge.
Disables address acknowledge.
FUJITSU SEMICONDUCTOR LIMITED
4 3
ALE SPF
R/W R/W
0 0
2
C address matches the slave address. Clear the IBCR1n:INT
2
C operation (ICCRn:EN = 0).
Details
MB95630H Series
2 1
SPE WUF WUE
R/W R/W
0 0
MN702-00009-1v0-E
0
R/W
0