Fujitsu F2MC-16LX Hardware Manual page 15

21.6.1 Baud Rate of the UART Internal Clock Using the Dedicated Baud Rate Generator ......................501
21.6.2 Baud Rate of the External Clock Using the Dedicated Baud Rate Generator ................................502
21.6.3 Baud Rate of the External Clock (One-to-one Mode).....................................................................503
21.7 Explanation of Operation of UART ......................................................................................................504
21.7.1 Operation in Asynchronous Mode (Operation Mode 0 or Operation Mode1) .................................506
21.7.2 Operation in Synchronous Mode (Operation Mode 2)....................................................................509
21.7.3 Bidirectional Communication Function (Normal Mode) ..................................................................512
21.7.4 Master/Slave Mode Communication Function (Multi-processor Mode) ..........................................514
21.8 Notes on Using UART .........................................................................................................................517
21.9 Example of UART Programming .........................................................................................................518
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CHAPTER 22 I C INTERFACE ..........................................................................................521
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22.1 I C Interface Outline ............................................................................................................................522
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22.2 I C Interface Register ..........................................................................................................................524
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22.2.1 I C Bus Status Register 0 to 2 (IBSR0 to IBSR2) ..........................................................................525
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22.2.2 I C Bus Control Register 0 to 2 (IBCR0 to IBCR2).........................................................................527
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22.2.3 I C Bus Clock Control Register 0 to 2 (ICCR0 to ICCR2) ..............................................................532
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22.2.4 I C Bus Address Register 0 to 2 (IADR0 to IADR2) .......................................................................534
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22.2.5 I C Bus Data Register 0 to 2 (IDAR0 to IDAR2).............................................................................535
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22.3 I C Interface Operation........................................................................................................................536
22.3.1 Transfer Flow of I
22.3.2 Mode Flow of I
22.3.3 Operation Flow of I
CHAPTER 23 ROM MIRROR FUNCTION SELECTION MODULE ...................................543
23.1 Overview of ROM Mirror Function Select Module ...............................................................................544
23.2 ROM Mirror Function Select Register (ROMM) ...................................................................................545
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION............................................547
24.1 Overview of Address Match Detection Function..................................................................................548
24.2 Block Diagram of Address Match Detection Function .........................................................................549
24.3 Configuration of Address Match Detection Function ...........................................................................550
24.3.1 Address Detection Control Register (PACSR) ...............................................................................551
24.3.2 Detect Address Setting Registers (PADR0, PADR1) .....................................................................553
24.4 Explanation of Operation of Address Match Detection Function .........................................................555
24.4.1 Example of Using Address Match Detection Function ...................................................................556
24.5 Program Example of Address Match Detection Function ....................................................................561
CHAPTER 25 3M-BIT FLASH MEMORY...........................................................................563
25.1 Overview of 3M-bit Flash Memory .......................................................................................................564
25.2 Sector Configuration of 3M-bit Flash Memory .....................................................................................565
25.3 Flash Memory Control Status Register (FMCS) ..................................................................................566
25.4 Automatic Algorithm Initiation Method of Flash Memory .....................................................................569
25.5 Check the Execution State of Automatic Algorithm .............................................................................570
25.5.1 Data Polling Flag (DQ7) .................................................................................................................572
25.5.2 Toggle Bit Flag (DQ6).....................................................................................................................573
25.5.3 Timing Limit Over Flag (DQ5).........................................................................................................574
25.5.4 Sector Erasing Timer Flag (DQ3) ...................................................................................................575
25.5.5 Toggle Bit 2 Flag (DQ2)..................................................................................................................576
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C Interface ........................................................................................................538
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C Interface.............................................................................................................540
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C Interface ......................................................................................................541
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