Fujitsu F2MC-16LX Hardware Manual page 496

CHAPTER 21 UART
Serial input data register 0 to 3 (SIDR0 to SIDR3)
The register retains the receive data. The serial input is converted and then stored in this register.
Serial output data register 0 to 3 (SODR0 to SODR3)
The register sets the transmit data. Data written to this register is serially converted to be output.
UART prescaler control register 0 to 3 (UTCR0 to UTCR3)
Specifies start-up/halt of the communication prescaler, forced reset of UART, selecting of clock sources,
and the rate of division of the machine clock.
UART prescaler reload register 0 to 3 (UTRLR0 to UTCR3)
Specifies the division rate of the machine clock.
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