Ep0 To Ep5 Data Register (Ep0Dt To Ep5Dt) - Fujitsu F2MC-16LX Hardware Manual

13.3.10

EP0 to EP5 Data Register (EP0DT to EP5DT)

The EP0 to EP5 data registers (EP0DT to EP5DT) are access registers used to read or
write into the transmission/receive buffer for transfer data related to EndPoint0 to
EndPoint5.
EP0 to EP5 Data Register (EP0DT to EP5DT)
Figure 13.3-12 shows the bit configurations of the EP0 to EP5 data registers (EP0DT to EP5DT).
Figure 13.3-12 EP0 to EP5 Data Register (EP0DT to EP5DT)
Address bit 7
EP0DT 0000F0
H
EP1DT 0000F2
H
X
EP2DT 0000F4
H
R/W
EP3DT 0000F6
H
EP4DT 0000F8
H
EP5DT 0000FA
H
15
Address bit
EP0DT 0000F1
H
EP1DT 0000F3
H
X
EP2DT 0000F5
H
R/W
EP3DT 0000F7
H
EP4DT 0000F9
H
EP5DT 0000FB
H
The following describes the function of each bit in the EP0 to EP5 data registers (EP0DT to EP5DT).
[bit 15 to bit 0] BFDT: EndPoint transmission/receive buffer data bit
It is a data read and data write register for the transmission/receive buffer for each EndPoint. Access to
the BFDT register via DMA transfer is supported on a word access only. If you transfer the odd number
of pieces of data through DMA transfer, you can do so by setting a byte transfer for the last data
transfer. If you perform word transfer via CPU access, the last transfer must be byte transfer the same
way as in DMA transfer.
Note:
CPU access to the EP0DT to EP5DT registers are possible both on a per-byte basis and on a per-
word basis, and if you byte access any of the registers, first, access bit 7 to bit 0, then access bit 15
to bit 8, and subsequently access the high-order and low-order alternately. Accessing the EP0DT to
EP5DT registers via bit instruction is prohibited.
6 5 4
BFDT
X X X
R/W R/W R/W
14 13 12
BFDT
X X X
R/W R/W R/W
3 2 1
X X X
R/W R/W R/W
11 10 9
X X X
R/W R/W R/W
CHAPTER 13 USB FUNCTION
0
←
X
Initial value
←
R/W
bit property
8
←
X
Initial value
←
R/W
bit property
295