Fujitsu F2MC-16LX Hardware Manual page 251

Table 11.3-1 Each Bit Functions of Watch Timer Control Register (WTC)
Bit name
WDCS:
bit 7 Watchdog timer clock
source selection bit
SCE:
Sub clock oscillation
bit 6
stabilization wait time
end bit
WTIE:
bit 5 Watch timer interval
interrupt enable bit
WTOF:
bit 4 Watch timer interrupt
request flag bit
WTR:
bit 3
Watch counter clear bit
bit 2 WTC2,WTC1,WTC0:
bit 1 Watch timer interval
bit 0 selection bit
• This bit selects the clock source of the watchdog timer.
• Watch timer clock is selected if this bit is "0", and otherwise timebase timer clock is
selected if this bit is "1".
• Initialized to "1" by a reset.
• It is a bit that indicates the oscillation stabilization wait time for the sub clock ends.
• When this bit is "0", it indicates that the oscillation stabilization wait time is elapsing.
• The oscillation stabilization wait time for the sub clock is fixed to 2
cycles.
• Initialized to "0" upon power-on reset and upon stop.
• This bit enables an interval interrupt by the watch timer.
• Interrupt is enabled if this bit is "1", and otherwise it is disabled if this bit is "1".
• Initialized to "0" by a reset.
• This bit indicates that an interrupt request of the watch timer has occurred.
• When the WTIE bit is 1 and this bit is set to "1", an interrupt request is generated.
• It is set to "1" at every interval set with the WTC2 to WTC0 bits.
• It is cleared with "0" by writing "0" into it, shifting to stop mode, and reset operation.
• Writing "1" does not have the meaning.
• This bit clears all bits of the watch timer counter.
• The watch timer counter is cleared to "0" by writing "0".
• Writing "1" does not have the meaning.
• The bit always returns "1" when read.
• It is a bit by which the interval of the watch timer is set.
• Initialized to "000
" by reset.
B
• To change the WTC2, WTC1, and WTC0 bits, clear the WTOF bit at the same time.
CHAPTER 11 WATCH TIMER
Functions
14
sub clock
235