Fujitsu F2MC-16LX Hardware Manual page 73

Figure 3.3-2 Interrupt Control Register (ICR00 to ICR15) at Read
At read
Address
MSB
0000B0
H
to
S1
0000BF
H
MSB : The most significant bit
LSB
: The least significant bit
: Undefined
: Initial value
LSB
S0 ISE IL2 IL1 IL0
IL2 IL1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
ISE
0
Activate interrupt sequence during generation of an interrupt.
1
Activate EI
S1 S0
0 0
0 1
1 0
1 1
CHAPTER 3 INTERRUPT
Initial value
- - 000111
B
IL0
Interrupt level set bit
0
Interrupt level 0 (Highest)
1
0
1
0
1
0
Interrupt level 7 (No interrupt)
1
2
EI OS enable bit
2
OS during generation of an interrupt.
2
EI OS status
2 2
EI OS operation in progress or EI OS not activated
Stop status by count end
Reserved
Stop status by request from peripheral function
57