Fujitsu F2MC-16LX Hardware Manual page 189

Oscillation Stabilization Wait Time
Oscillation Stabilization Wait Time of oscillation clock
Because the oscillator for original oscillation is stopped in stop mode, the oscillation stabilization wait time
must be required. For the oscillation stabilization wait time, you take the time selected in the oscillation
stabilization wait time selection bit (WA1, WA0) of the clock selection register (CKSCR).
Note:
Be sure to set "00
register ONLY at the time of the main clock.
Oscillation stabilization wait time of PLL clock
When the transition is made from a state where the CPU is operated by the main clock and the PLL clock
halts, to a mode where CPU and the peripherals are operated by the PLL clock, transition to the PLL clock
oscillation stabilization wait state is made and it is operated by the main clock during the oscillation
stabilization wait state.
The PLL clock oscillation stabilization wait time is fixed to 2
In sub-clock mode, the main clock and PLL multiplication circuit stop. When changing to PLL clock mode,
it is necessary to reserve the main clock oscillation stabilization wait time and PLL clock oscillation
stabilization wait time. The oscillation stabilization wait times for main clock and PLL clock are counted
simultaneously according to the value specified in the oscillation stabilization wait time selection bits
(CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection bits
(CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer
of the main clock and PLL clock oscillation stabilization wait times. The PLL clock oscillation stabilization
wait time, however, requires 2
(CKSCR: WS1, WS0) in the clock selection register to "10
In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop
mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation
stabilization wait time. The oscillation stabilization wait times for main clock and PLL clock are counted
simultaneously according to the value specified in the oscillation stabilization wait time selection bits
(CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection bits
(CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer
of the main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation stabilization
wait time, however, requires 2
(CKSCR: WS1, WS0) in the clock selection register to "10
Switching Clock Mode
When switching of the clock mode is made, be sure not to change to other clock modes or the low-power
consumption mode until the completion of the switching. Completion of the switching can be checked by
referencing the MCM and SCM bits of the CKSCR. If the mode is switched to another clock mode or low-
power-consumption mode before completion of switching, the mode may not be switched.
" for the oscillation stabilization wait time selection bit (WS1, WS0) of the CKSCR
B
14
/HCLK or more. Set the oscillation stabilization wait time selection bits
14
/HCLK or more. Set the oscillation stabilization wait time selection bits
CHAPTER 6 LOW-POWER CONSUMPTION MODE
14
/HCLK (HCLK: oscillation clock).
" or "11 ".
B B
" or "11 ".
B B
173