Fujitsu F2MC-16LX Hardware Manual page 440

CHAPTER 18 DTP/EXTERNAL INTERRUPT
DTP/Interruption Factor Register (EIRR: External Interrupt Request Register)
Figure 18.2-3 shows the bit configuration of DTP/interruption factor register (EIRR).
Figure 18.2-3 Bit Configuration of DTP/interruption Factor Register (EIRR)
EIRR
Address : 00003D
The DTP/interrupt factor register (EIRR) indicates the presence of corresponding external DTP/interrupt
request when reading and clears the flip-flop contents that indicates this request when writing. When "1" is
read from the EIRR register it indicates the external DTP/interrupt request presence in a terminal
corresponding to the ERx bit. In addition, when "0" is written in the EIRR register, the request flip-flop of
the corresponding bit is cleared. Writing "1" causes no operation. "1" is read with a read-modify-write
instruction.
Notes:
• The initial value is "00h" while the value is changed after the reset depending on the status of
terminal in the common-use with the external interrupt.
• Clear only the bits that the CPU accepted the interrupt (those bits that ER7 to ER0 are set to "1")
to "0" when plural external interrupt request outputs are enabled (ENIR: EN7 to EN0 = 1). No
other bits must be cleared unconditionally.
Request Level Setting Register (ELVR: External Level Register)
Figure 18.2-4 shows the bit configuration of the request level setting register (ELVR).
ELVR
Address : 00003E
Address : 00003F
The request level setting register (ELVR) selects the request detection level. Two bits are allocated per
terminal as shown in Table 18.2-1. When the request input is in the level mode and the input is active, it is
again set even if it is cleared.
Table 18.2-1 ELVR allocation (LA0-LA7,LB0-LB7)
LBx
0
0
1
1
424
15 14 13 12
ER7 ER6 ER5 ER4
H
R/W R/W R/W R/W
Figure 18.2-4 Request Level Setting Register (ELVR)
7 6
LB3 LA3
H
R/W R/W
15 14
LB7 LA7
H
R/W R/W
LAx
0
1
0
1
11 10 9 8
ER3 ER2 ER1 ER0
R/W R/W R/W R/W
5 4 3 2
LB2 LA2 LB1 LA1
R/W R/W R/W R/W
13 12 11 10
LB6 LA6 LB5 LA5
R/W R/W R/W R/W
Operation
There is a demand at "L" level.
There is a demand at "H" level.
Request present at the rising edge
Request present at the falling edge
Initial value
00000000
B
(However, the object is different
between both of them.)
1 0
Initial value
LB0 LA0
00000000
B
R/W R/W
9 8
Initial value
LB4 LA4
00000000
B
R/W R/W