Fujitsu F2MC-16LX Hardware Manual page 81

Operation of Hardware Interrupt
Figure 3.4-2 shows the operation sequence from generation of a hardware interrupt to completion of
interrupt handling.
Internal bus
(7)
(8)
IL : Interrupt level set bit of Interrupt control register (ICR)
PS : Processor status
I : Interrupt enable flag
ILM: Interrupt level mask register
IR : Instruction register
FF : flip - flop
(1) An interrupt cause occurs in a peripheral function.
(2) The peripheral function interrupt enable bit is referred. If it indicates "enable", an interrupt request is
output from the periphery to the interrupt controller.
(3) After receiving the interrupt request, the interrupt controller determines the priorities of the
simultaneously received interrupt requests. Then, the controller sends the ILs associated with the
interrupt requests to the CPU.
(4) The CPU compares the interrupt level requested from the interrupt controller with the interrupt level
mask register (ILM).
(5) If the comparison reveals that the priority is higher than the current interrupt handling level, the contents
of the I flag of the condition code register (CCR) will be checked.
(6) If the check in Item 5) reveals that the I flag indicates "enable", that is, I = 1, control waits for
completion of the currently active instruction. The requested IL is set in the ILM on completion.
(7) The contents of the register are saved before control branches to the interrupt handling routine.
(8) The software in the interrupt handling routine clears the interrupt cause generated at 1 and executes the
RETI instruction to complete the interrupt handling.
Figure 3.4-2 Operation of Hardware Interrupt
PS, PC
Microcode
2
F MC-16LX CPU
Other peripheral
function
Peripheral function generated
Interrupt request
Enable FF
AND
Factor FF
(1)
RAM
PS I
IR
Check
(6)
(5)
(2)
CHAPTER 3 INTERRUPT
ILM
Comparator
(4)
(3)
Level Interrupt
comparator level IL
Interrupt controller
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