Fujitsu F2MC-16LX Hardware Manual page 489

16-bit microcontroller mb90330 series

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Figure 20.3-5 When Instruction Shift is Performed in the External Shift Clock Mode.

Stop by STOP=1 (LSB first, At internal clock)

Figure 20.3-6 Stop Timing when STOP Bit is Assumed to be "1"

Operation during Transfer Serial Data

During transferring serial data, data from the serial output terminal (SOT) is output on the falling edge of

the shift clock, data of the serial input terminal (SIN) is input on the rising edge.

LSB first (when BDS bit is set to "0")

MSB first (when BDS bit is set to "1")

SCK bit "0" of PDR

When Mode = 0

(Transfer start)

Figure 20.3-7 Shift Timing of I/O (LSB First)

Figure 20.3-8 Shift Timing of I/O (LSB First)

CHAPTER 20 EXTENDED I/O SERIAL INTERFACE

SCK bit "0" of PDR

SCK bit "1" of PDR

(Transfer end)

(Transfer complete)