Fujitsu F2MC-16LX Hardware Manual page 261

[bit 5] STOP (Timer operation stop bit)
It is bit for stopping count of 16-bit free-run timer. Writing "1" into this bit stops counting the 16-bit
free-run timer and writing "0" starts counting it.
0 Count permission (operation)
1 Count disabled (Stop)
Note that the output compare operation will stop when the 16-bit free-run timer stops counting.
[bit 4] MODE (Clear condition selection bit)
This bit specifies the initialization conditions of the 16-bit free-run timer.
If this bit is "0", the value of the count can be initialized with reset operation and clear bit ((CLR) of bit
2).
If this bit is "1", the value of the count can be initialized with reset operation and clear bit ((CLR) of bit
2), and through matching the value of the compare clear register in the output compare.
0 Initialization by reset and clear bit
1 Initialization by a reset, clear bit or the compare clear register.
Further, note that the value of the counter is initialized on the point of change in the count value.
[bit 3] CLR (Timer clear bit)
This bit initializes the value of the 16-bit free-run timer to "0000
Writing "1" into the bit initializes the value of the counter to "0000
meaning. This bit is always "0" at the beginning of reading. The value of the counter is initialized on the
point of change in the counter value.
0 No meaning.
1 The counter value is initialized to "0000
Note that you must write "0000
timer is stopped.
"
H
" into the data register if you want to initialize the counter value while the
H
CHAPTER 12 16-BIT I/O TIMER
[Initial value]
[Initial value]
" while it is operating.
H
". Writing "0" into the bit has no
H
[Initial value]
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