Fujitsu F2MC-16LX Hardware Manual page 436

CHAPTER 17 8/16-BIT PPG TIMER
Writing Timing to Reload Register
In any modes other than the 16-bit PPG mode, the word transfer instruction is recommended to write data
into the reload registers PRLL and PRLH. When the data item is written in the register by using the byte
transfer instructions for two times, an unexpected pulse width output may be generated depending on the
timing.
Figure 17.3-3 shows the timing for writing in reload register.
PPG0
In Figure 17.3-3, when the PRLL is updated from A to C before the [1] timing and the PRLH value is
updated from B to D after the [1] timing, the PRL values at the [1] timing are represented as PRLL = C and
PRLH = B to generate pulses of the count number C for the L side and the count number B for H side only
once. Similarly, in order to write data in the PRL of ch0/ch2/ch4 and ch1/ch3/ch5 in the 16-bit PPG mode,
the long-word transfer instruction is used or the word transfer instruction is sequentially used for the PRL
of the ch0 → ch1 (ch2 → ch3/ch4 → ch5). In this mode, the data are temporally written from the ch0/ch2/
ch4 to the PRL. Then, when they are written in the PRL of ch1/ch3/ch5, they actually written in the PRL of
ch0.
In modes other than the 16-bit PPG mode, data can be written independently to the ch0/ch2/ch4 and ch1/
ch3/ch5.
Figure 17.3-4 shows the block diagram of writing to PRL register.
Writing data of PRL of ch0
Writing to ch0
other than
16-bit PPG mode
420
Figure 17.3-3 Timing Chart for Writing in Reload Register
A B A
Figure 17.3-4 Block Diagram of Writing to PRL Register
Temporary latch
PRL of ch0
B C B C
[1]
Writing data of PRL of ch1
Synchronize with writing
to ch1 at 16-bit PPG mode
and transfer
D C D
Written data of ch1
PRL of ch1