Fujitsu F2MC-16LX Hardware Manual page 576

CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION
Flow of Patch Processing
Figure 24.4-5 shows the flow of patch processing using the address match detection function.
0 0 0 0 0 0
0 0 0 1 0 0
0 0 0 4 0 0
0 0 0 4 8 0
0 0 0 9 0 0
F F 0 0 0 0
F F 8 0 0 0
F F 8 0 5 0
FFFFFF
560
Figure 24.4-5 Flow of Patch Processing
MB90330 series
I/O area
H
Register/RAM area
H
Patch program
H
RAM area
H RAM
Stack area
H
Detection address setting register
H
Program error
H
H
H
Reset
Read the 00
H
2
of E PROM
YES
2
E PROM : 0000
H
= 0
NO
Read detect address
2
E PROM : 0001 to 0003
H H
↓
MCU : Set to PADR0
Read patch program
2
E PROM : 0010 to 008F
H H
↓
MCU : 000400 to 00047F
H H
Enable address match detection
(PACSR : AD0E = 1)
Execution of normal
program
NO YES
Program address
PC= PADR0
0000
Patch program byte count : 80
H
0001
Detect address (Low) : 00
H
0002 Detect address (Middle) : 80
H
0003
Detect address (High) : FF
H
0010
H
0090
H
FFFF
H
ROM
Branch to patch program
JMP 000400
Execution of patch program
000400
End of patch program
JMP FF8050
INT9
2
E PROM
H
H
H
H
Patch program
INT9
H
to 000480
H H
H