Fujitsu F2MC-16LX Hardware Manual page 407

[bit 5] OUTL (setting of output level)
This bit is used to set the TOT0 to TOT2 pin output level. OUTL and the output pin level reverses in 0/
1.
OUTL At One-shot mode (RELD=0)
0 Short-shape wave during counting "H"
1 Short-shape wave during counting "L"
X
X
[bit 4] RELD (reload operation permission)
It is a bit by which the reload operation is permitted. When the RELD is "1", the timer operates in the
reload mode operation. In this mode, the timer loads the reload register content to the counter and
continues the count operation even when an underflow occurs (when the counter value changes from
0000 to FFFF ). The timer works in the single shot mode when RELD is "0". In this mode, the
H H
counter operation stops when the counter value changes from 0000
occurs.
RELD
0 One-shot mode [Initial value]
1 Reload mode
[bit 3] INTE (timer interruption demand permission)
This bit permits the timer interrupt request. If the INTE value is 0, no interrupt request is generated even
when the UF value becomes "1".
INTE
0 Interrupt request power output interdiction [Initial value]
1 Interrupt request output enabled
[bit 2] UF (timer interruption demand flag)
It is Interrupt request flag. When the underflow is generated, UF is set in "1". Cleared by writing "0" or
by µDMAC. The read value is "1" when using a read-modify-write instruction.
UF
Underflow none of counter
0
[Initial value]
There is an underflow of the
1
counter.
At Reload mode (RELD=1)
1
1
Function
Function
At write
CHAPTER 16 16-BIT RELOAD TIMER
0 [Initial value]
1
0
1
to FFFF
H
At programming
Clearness of this bit [Initial value]
There is no change
(There is no influence on another).
and the underflow
H
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