Fujitsu F2MC-16LX Hardware Manual page 14

18.4 Precaution of Using DTP/External Interrupt........................................................................................ 427
CHAPTER 19 8/10-BIT A/D CONVERTER........................................................................429
19.1 Overview of 8/10-bit A/D Converter .................................................................................................... 430
19.2 Configuration of 8/10-bit A/D Converter.............................................................................................. 431
19.3 Register of 8/10-bit A/D Converter...................................................................................................... 433
19.3.1 A/D Control Status Register (High) (ADCS1)................................................................................. 434
19.3.2 A/D Control Status Register (Low) (ADCS0) ................................................................................. 436
19.3.3 A/D Conversion Channel Set Register (ADMR)............................................................................. 438
19.3.4 A/D Data Register (ADCR1/ADCR0) ............................................................................................. 440
19.4 Explanation of Operation of 8/10-bit A/D Converter............................................................................ 442
19.4.1 Conversion Operation Using µDMAC or EI
19.4.2 A/D-converted Data Protection Function ....................................................................................... 446
19.5 Precautions when Using 8/10-bit A/D Converter ................................................................................ 448
19.6 Example of program-1 of 8/10-bit A/D Converter
(Example of Starting the EI
19.7 Example of Program-2 of 8/10-bit A/D Converter
(Example of Starting the EI
19.8 Example of Program-3 of 8/10-bit A/D Converter
(Example of Starting the EI
CHAPTER 20 EXTENDED I/O SERIAL INTERFACE .......................................................459
20.1 Outline of Extended I/O Serial Interface ............................................................................................. 460
20.2 Register in Extended I/O Serial Interface............................................................................................ 461
20.2.1 Serial Mode Control Status Register (SMCS)................................................................................ 462
20.2.2 Serial Data Register (SDR)............................................................................................................ 466
20.2.3 Communication Prescaler Control Register (SDCR) ..................................................................... 467
20.3 Operation of Extended I/O Serial Interface ......................................................................................... 468
20.3.1 Shift Clock Mode............................................................................................................................ 469
20.3.2 Operation State of Serial I/O.......................................................................................................... 470
20.3.3 Start/stop Timing of Shift Operation and Timing of I/O .................................................................. 472
20.3.4 Interrupt Function........................................................................................................................... 474
CHAPTER 21 UART ..........................................................................................................475
21.1 Overview of UART .............................................................................................................................. 476
21.2 UART Block Diagram.......................................................................................................................... 478
21.3 UART Pins .......................................................................................................................................... 481
21.4 Register of UART................................................................................................................................ 482
21.4.1 Serial Control Register 0 to 3 (SCR0 to SCR3) ............................................................................. 483
21.4.2 Serial Mode Register 0 to 3 (SMR0 to SMR3) ............................................................................... 485
21.4.3 Serial Status Register 0 to 3 (SSR0 to SSR3) ............................................................................... 487
21.4.4 Serial Input Data Register 0 to 3(SIDR0 to SIDR3) and
Serial Output Data Register0 to 3(SODR0 to SODR3).................................................................. 490
21.4.5 UART Prescaler Control Register 0 to 3 (UTCR0 to UTCR3) and
UART Prescaler Reload Register 0 to 3 (UTRLR0 to UTRLR3).................................................... 492
21.5 UART Interrupt.................................................................................................................................... 494
21.5.1 Receive Interrupt Generation and Flag Set Timing........................................................................ 496
21.5.2 Transmit Interrupt Generation and Flag Set Timing....................................................................... 498
21.6 UART Baud Rate ................................................................................................................................ 500
2
OS............................................................................. 445
2
OS in the Single Mode) .......................................................................... 449
2
OS in the Continuous Mode) .................................................................. 452
2
OS in the Stop Mode)............................................................................. 455
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