Fujitsu F2MC-16LX Hardware Manual page 621

Table A-1 I/O Map (4/9)
Address
000061
H
000062
H
Timer control status register 0
000063
H
Low order of 16-bit timer register 0
000064
H
Low order of 16-bit reloading 0
High order of 16-bit timer register 0
000065
H
High order of 16-bit reloading 0
000066
H
Timer control status register 1
000067
H
Low order of 16-bit timer register 1
000068
H
Low order of 16-bit reloading 1
High order of 16-bit timer register 1
000069
H
High order of 16-bit reloading 1
00006A
H
Timer control status register 2
00006B
H
Low order of 16-bit timer register 2
00006C
H
Low order of 16-bit reloading 2
High order of 16-bit timer register 2
00006D
H
High order of 16-bit reloading 2
00006E
H
00006F
ROM Mirroring Function Select Register
H
2
000070
I C bus status register 0
H
2
000071
I C bus control register 0
H
2
000072
I C bus clock control register 0
H
000073 2
I C bus address register 0
H
2
000074
I C bus data register 0
H
000075
H
000076 2
I C bus status register 1
H
2
000077
I C bus control register 1
H
000078 2
I C bus clock control register 1
H
2
000079
I C bus address register 1
H
00007A 2
I C bus data register 1
H
00007B
H
Registers Abbreviation Access
Use prohibited
TMCSR0 R/W
TMR0 R
TMRLR0 W
TMR0 R
TMRLR0 W
TMCSR1 R/W
TMR1 R
TMRLR1 W
TMR1 R
TMRLR1 W
TMCSR2 R/W
TMR2 R
TMRLR2 W
TMR2 R
TMRLR2 W
Use prohibited
ROMM R/W,W
IBSR0 R
IBCR0 R/W
ICCR0 R/W
IADR0 R/W
IDAR0 R/W
Use prohibited
IBSR1 R
IBCR1 R/W
ICCR1 R/W
IADR1 R/W
IDAR1 R/W
Use prohibited
Appendix A Memory Map
Release Initial value
00000000
16bit reload timer
ch0
XXXX0000
XXXXXXXX
XXXXXXXX
16bit reload timer
ch0
XXXXXXXX
XXXXXXXX
00000000
XXXX0000
16bit reload timer
XXXXXXXX
ch1
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000000
XXXX0000
16bit reload timer XXXXXXXX
ch2
XXXXXXXX
XXXXXXXX
XXXXXXXX
ROM mirror
------11
function
00000000
00000000
2
XX0XXXXX
I C interface ch0
XXXXXXXX
XXXXXXXX
00000000
00000000
2
XX0XXXXX
I C interface ch1
XXXXXXXX
XXXXXXXX
605