Fujitsu F2MC-16LX Hardware Manual page 448

CHAPTER 19 8/10-BIT A/D CONVERTER
A/D control status registers (ADCS)
Displayed are the start and start trigger selection by software, the conversion mode selection, the A/D
conversion channel selection, the enabled and disabled interrupt requests, the interrupt request status
confirmation, the suspension status and the conversion status.
A/D data registers (ADCR)
This register stores the A/D conversion result and also has a function to select the A/D conversion
resolution.
A/D conversion channel set register (ADMR)
This register selects the A/D conversion channel.
Decoder
This circuit selects the analog input terminal to be used from the setting of bits from ANE0 to ANE3 and
from ANS0 to ANS3 of A/D conversion channel set register (ADMR).
Analog channel selector
This circuit selects the terminal to be used from the 16 analog input terminals.
Sample hold circuit
This circuit holds the input voltage selected by the analog channel selector. The input voltage can be
converted without affected by the input voltage fluctuation in the A/D conversion (in the comparison) by
holding the sample of input voltage immediately after starting the A/D conversion.
D/A converter
The reference voltage is generated to compare the held sample of input voltage.
Comparator
This compares the input voltage for which sample hold is performed, with the output voltage of the D/A
converter to determine which is the greater of the two.
Control circuit (Sequential comparison register)
The signal from the comparator (higher or lower) determines the A/D conversion value. When the A/D
conversion is terminated, the conversion result is stored in the A/D data register (ADCR) and the interrupt
request is generated.
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