Udc Status Register (Udcs) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 13 USB FUNCTION
13.3.5

UDC Status Register (UDCS)

The UDC status register (UDCS) is a register that indicates the status of a bus on USB
communications and a particular command received. Each bit in the register except
SETP indicates an interrupt factor and raises an interrupt to CPU if its corresponding
interrupt enable bit is specified and valid.
UDC Status Register (UDCS)
Figure 13.3-7 shows the bit configurations of the UDC status register (UDCS).
Address bit 7
0000E0 VOFF
H
0
0
R/W
The function of each bit in the UDC status register (UDCS) is described in the following.
[bit 7] VOFF:VBUS cutting detection bit
The detection of the USB cable cutting is shown. It is set if VBUS changes from being connected ("H"
level kept detecting for not less than 2.6 µs) to 2.6 µs continuous application of the "L" level potential.
The VOFF bit is a interrupt factor and writing "1" is ignored. Please clear by writing "0". "1" is read at
the read modification write.
VOFF
0
1
Note:
The level detection of VBUS is done by 12 MHz sampling. Therefore, VBUS changes for less than
about 83 ns may not be detected.
280
Figure 13.3-7 UDC Status Register (UDCS)
6 5 4
VON SUSP SOF
0 0 0
Irrelevance 0 0
R/W R/W R/W
VBUS is a stationary state.
Cutting USB is detected.
3 2 1
BRST WKUP SETP
0 0 0
0 0 0
R/W R/W R/W
Operating mode
0
CONF UDC status register
←
0
Initial value
←
0
RST Reset
←
R/W
Access