Fujitsu F2MC-16LX Hardware Manual page 527

16-bit microcontroller mb90330 series

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[Serial control register 0 to 3 (SCR0 to SCR3)]

P, SBL, and A/D : These bits do not have the meaning.

[Serial Status Register 0 to 3 (SSR0 to SSR3)]

Starting communications

When the sending data is written in the serial output data registers 0 to 3 (SODR0 to SODR3),

communication starts. To start communication, temporal sending data must be written to the serial output

data registers 0 to 3 (SODR0 to SODR3) even when only receiving operation is necessary.

Terminating communications

As soon as one frame of data is sent and received, the receiving data full flag bit (SSR0 to SSR3: RDRF) is

set to "1". Having received the data, check the overrun error flag bit (SSR0 to SSR3: ORE) to ensure that

the communication was successfully done.

: "1"(8-bit data)

: "0" (for initialization, error flags cleared).

: At least, it is "1" as for either

: "1" to use interrupts, "0" not to use interrupts.

CHAPTER 21 UART