Operation Of Dtp/External Interrupt - Fujitsu F2MC-16LX Hardware Manual

18.3

Operation of DTP/External Interrupt

This section describes the Operation of DTP/External Interrupt.
External Interrupt Operation
If a request set by the ELVR register at the corresponding terminal is input after setting an external
interrupt request, this resource issues an interrupt request signal for the interrupt controller. When the
interrupt from this resource had the highest priority as a result of the priority identification of the interrupts
simultaneously occurred in the interrupt controller, the interrupt controller issues an interrupt request to the
2
F MC-16LX CPU. The F
processor status (PS) with the interrupt request. When the request level is higher than the ILM bit, the
hardware interrupt process microprogram is started as soon as the current instruction execution is
terminated.
Figure 18.3-1 shows the external interrupt operation flow.
External interrupt/DTP
Factor
The interrupt process microprogram reads the interrupt vector area, issues the interrupt acknowledge to the
interrupt controller, transfers the macro instruction jump address generated by the vector to the program
counter, and executes the user interrupt process program.
Operation of DTP
As an initialization in the user program before starting the µDMAC, the register addresses allocated in from
000000
H
start address is set to the buffer address pointer.
The DTP operation sequence is almost same with those of external interrupt and are quite identical until the
CPU starts the hardware interrupt process microprogram. When the µDMAC is started, the read or write
signal is sent to the addressed external peripheral device for the transfer operation with this chip. The
external peripheral device must cancel the interrupt request to this chip within three machine cycles after
the transfer operation. When the transfer is terminated, the descriptor, etc. are updated and the interrupt
controller generates the signal to clear the transfer factor. When this resource receives the signal to clear the
transfer factor, it clears the flip-flop that holds the factor and prepares for the next terminal request.
Figure 18.3-2 shows the timing to cancel the external interrupt request at the DTP operation termination.
In addition, Figure 18.3-3 shows the example of interfaces with external peripheral devices.
2
MC-16LX CPU compares the interrupt level mask register (ILM) in the
Figure 18.3-1 External Interrupt Operation
Other
requests
ELVR
EIRR
ENIR
are set to the I/O address pointer in the µDMAC descriptor and the memory buffer
to 0000FF
H
CHAPTER 18 DTP/EXTERNAL INTERRUPT
Inrerrupt controller
ICR
yy
CMP
ICR
xx
2
F MC-16LXCPU
IL
CMP
ILM
INTA
425