Fujitsu F2MC-16LX Hardware Manual page 539

Block Diagram of I
Figure 22.1-1 shows the block diagram of I
ICCR
EN
ICCR
CS4
CS3
CS2
CS1
CS0
IBSR
BB
RSC
LRB
TRX
FBT
AL
IBCR
BER
BEIE
INTE
INT
IBCR
SCC
MSS
ACK
GCAA
IBSR
AAS
GCA
2
C Interface
Figure 22.1-1 Block Diagram of I
2
I C enable
Clock divider 1
5 6 7
Clock selection 1
Clock divider 2
2 4 8 16 32 64 128
Clock selection 2
Bus busy
Repeat start
Start
Last Bit
Condition detection
Send/
receive
Arbitration lost detection
Interrupt request
Start
Master
Start
ACK enable
Condition generation
GC-ACK enable
IDAR
Slave
Slave address
Gloval call
compare
IADR
2
C interface.
2
C Interface
Peripheral clock
8
Sync
256
Shift clock generaiton
Shift clock
edge change
timing
Stop
Error
First Byte
IRQ #17,19,21
End
Stop
2
CHAPTER 22 I C INTERFACE
SCL0 SCL2
to
SDA0 SDA2
to
523