Fujitsu F2MC-16LX Hardware Manual page 427

[bit 13] PE10: ppg output Enable10 (PPG1/PPG3/PPG5 output pin enabled)
Inhibition and permission of pulse output to the external pulse output pin PPG1/PPG3/PPG5 are
controlled.
PE10
0 General-purpose port pin (pulse output interdiction)
1 PPG1/PPG3/PPG5 pulse output (pulse output permission)
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[bit 12] PIE1: ppg Interrupt Enable (interrupt to PPG1/PPG3/PPG5 enabled)
PPG1/PPG3/PPG5 interrupt inhibition and permission are controlled.
PIE1
0 Disables the interrupt.
1 Interruption permission.
• If PUF1 is set to "1" when this bit is "1", an interrupt request is generated. When this bit is "0", no
interrupts are generated.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[bit 11] PUF1:Ppg Underflow Flag (PPG1/PPG3/PPG5 counter underflow)
Detected result of counter underflow of the PPG1/PPG3/PPG5 is shown.
PUF1
0 The PPG counter underflow has not been detected.
1 The PPG counter underflow was detected.
In the 8-bit PPG6 channel mode (PPG0, PPG1/PPG2, PPG3/PPG4, PPG5) and the 8-bit prescaler + 8-bit
PPG mode, the counter values of ch1, ch3, ch5 are set to "1" when they underflow from 00
16-bit PPG3 channel mode (PPG0, PPG1/PPG2, PPG3/PPG4, PPG5), the counter values of ch1, ch3, ch5/
ch0, ch2, ch4 are set to "1" when they underflow from 0000
writing in the PUF0 bit is not significant. "1" is read with a read-modify-write instruction.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
CHAPTER 17 8/16-BIT PPG TIMER
Operating State
Operating State
Operating State
to FFFF . Becomes "0" by written "0". "1"
H H
to FF . In the
H H
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