Udc Control Register (Udcc) - Fujitsu F2MC-16LX Hardware Manual

13.3.1

UDC Control Register (UDCC)

UDC control register (UDCC) controls the UDC core circuit.
UDC Control Register (UDCC)
Figure 13.3-3 shows the bit configuration of the UDC control register (UDCC).
Addressbit
0000D0 RST
H
R/W
Note:
You must set the UDC control register (UDCC) when RST of bit 7 is 1 except bit 6 or RESUM of bit 6
and USTP of bit 4, and never rewrite it while USB is operating. Set and reset RESUM of bit 6 only
when USB is in suspend status and gets in remote Wake-up enabled status with the following
command:
Set USTP of bit 4 to "1" before entering the stop mode state.
To deselect the stop mode, set the order of SUSP and USTP in the UDCS to "0".
The following describes the function of each bit in the UDC control register (UDCC).
[bit 7] RST: Function reset bit
Apply an individual reset that is equivalent to the system reset to the chip to the USB Function. Apply a
reset to the USB Function with the RST bit when connecting a cable to the HOST PC. Since the RST
bit has the initial value of "1" and the USB Function is in reset status, release the Function by writing
"0" to the bit.
RST
0
1
Note:
The RST bit initializes the corresponding bits of the timestamp register, UDC status register, and
interrupt enable register at once. In addition, since it sets EP0I, EP0O, and BFINIs of EP1 to EP5
status registers at the same time after initialization, clear the RST bit (which does not clear the BFINI
bits), and clear the BFINI of an endpoint to be used in this sequence.
Figure 13.3-3 UDC Control Register (UDCC)
7 6 5
RESUM HCON
1 0 1
R/W R/W
Reset of USB Function release
Reset USB Function
4 3 2
USTP Reserved Reserved
0 0 0
R/W R/W R/W
Operating mode
CHAPTER 13 USB FUNCTION
1 0
RFBK PWC UDC control register
←
0 0
Initial value
←
R/W R/W
Access
271