Flash Memory Control Status Register (Fmcs) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 25 3M-BIT FLASH MEMORY
25.3

Flash Memory Control Status Register (FMCS)

The flash memory control status register (FMCS), which is allocated in the flash
memory interface circuit, is used for writing/erasing on the flash memory.
Flash Memory Control Status Register (FMCS)
Figure 25.3-1 shows the bit configuration of the flash memory control status register (FMCS).
Figure 25.3-1 Bit Configuration of Flash Memory Control Status Register (FMCS)
Flash memory control status register (FMCS)
Address: 0000AE
The function of each bit in the flash memory control status register (FMCS) is described in the following.
[bit 7] INTE: INTerrupt Enable
Finishing writing/erasing on the flash memory allows the CPU to generate an interrupt.
If the INTE bit is "1" and the RDYINT bit is "1", an interrupt to the CPU is generated. If the INTE bit is
"0", the interrupt is not generated.
0
1
[bit 6] RDYINT: ReaDY INTerrupt
This is the bit representing the operation state of flash memory.
Completion of writing/erasing on the flash memory allows this bit to set to "1". After writing/erasing on
flash memory, it is not possible to write/erase to flash memory while the RDYINT bit is "0". After
writing/erasing is completed and "1" is set, writing/erasing to flash memory is possible.
Writing "0" clears to "0" and writing "1" is ignored. The completion timing of the flash memory
automatic algorithm (see "25.4 Automatic Algorithm Initiation Method of Flash Memory") sets to "1".
When the read modify write (RMW) instruction is used, "1" is always read.
0
1
566
7 6 5 4
INTE RDY
WE
RDYINT
H
R/W R/W R/W R
Interrupt disabled in writing/erasing end
Interruption permission by writing/erase end
During writing/the deletion operation execution
Completion of writing/erasing operation (occurrence of interrupt requests)
3 2 1 0
LPM1 LPM0
Reserved Reserved
R/W
W R/W W
Initial value
000X0000
B