Fujitsu F2MC-16LX Hardware Manual page 547

16-bit microcontroller mb90330 series

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*: When "arbitration lost" is detected, the MSS bit is set to "1" and then the AL bit is set to "1" without failure

after the time for three-bit data transmission at the I

• Example of occurrence of an interrupt (INT bit=1) upon detection of "AL bit=1"

When an instruction which generates a start condition is executed (setting the MSS bit to "1") with "bus busy"

detected (BB bit=1) and arbitration is lost, the INT bit interrupt occurs upon detection of "AL bit=1".

Figure 22.2-6 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" Occurs

Notes on Use of I

The following care should be taken to conflicts among SCC bit, MSS bit, and INT bit.

Writing to SCC bit, MSS bit, INT bit simultaneously causes conflicts of transferring the next bite, occurrence

of the start condition, and occurrence of the stop condition. The priority in this case is as follows.

The following byte forwarding and stop condition generation

If "0" is written in INT bit and "0" in MSS bit, writing "0" in MSS bit is preferred and the stop condition

The following byte forwarding and start condition generation

If "0" is written in INT bit and "1" in SCC bit, writing "1" in SCC bit is preferred and the start condition

Start condition generation and stop condition generation

Simultaneous writing is disabled that not only "1" is written in SCC bit but also "0" is written in MSS bit.

Start Condition

SLAVE ADDRESS

C Bus Control Register 0 to 2 (IBCR0 to IBCR2)

CHAPTER 22 I

C transfer frequency.

Interrupt in the ninth clock cycle

Clearing the AL bit by software

Releasing the SCL by clearing

the INT bit by software