Fujitsu F2MC-16LX Hardware Manual page 147

PLL multiplying circuit
The oscillation clock is multiplied by PLL oscillation and supplied to the CPU clock selector.
Clock selector
From the main and sub clocks, and the three PLL clocks, this selects the clock to be supplied to the CPU
and periphery clock control circuits.
Clock select register (CKSCR)
Switches between the oscillation and PLL clocks, selects the oscillation stabilization wait time, and selects
the PLL clock multiplier.
Oscillation stabilization wait time selector
A circuit which selects the oscillation stabilization wait time for the oscillation clock succeeding release of
the stop mode or a watchdog reset. Four timebase timer outputs are selected.
CHAPTER 5 CLOCK
131