Fujitsu F2MC-16LX Hardware Manual page 430

CHAPTER 17 8/16-BIT PPG TIMER
[bit 4 to bit 2] PCM2 to PCM0:ppg Count Mode (count clock selection)
These bits select the down counter operation clock of ch0, ch2, and ch4.
PCM2
0
0
0
0
1
1
• These bits are initialized to "000
• Reading and writing are allowed.
[bit 1, bit 0] Reserved bit
It is Reserved bit. Always set this bit to "00
414
PCM1 PCM0
0 0 Peripheral Clock (41.6 ns machine clock 24 MHz time) in surrounding
0 1 Peripheral Clock /2 (83.3 ns machine clock 24 MHz time) in surrounding
1 0 Peripheral Clock /4 (167 ns machine clock 24 MHz time) in surrounding
1 1 Peripheral Clock /8 (333 ns machine clock 24 MHz time) in surrounding
0 0 Peripheral Clock /16 (667 ns machine clock 24 MHz time) in surrounding
Input clock from time base counter
1 1
9
(2 × 167 ns=85 ms field oscillation 6 MHz time)
" at reset.
B
Operating mode
".
B