Fujitsu F2MC-16LX Hardware Manual page 495

Clock selector
Dedicated baud rate generator, selecting the send and receive clock from external input clocks.
Reception Control Circuit
The reception control circuit is configured with the reception bit counter, start bit detecting circuit, and
reception parity counter. The receive bit counter counts receiving data. Once this counter completes
receiving a piece of data based on the specified data length, then a receiving interrupt request is generated.
The start bit detection circuit is a circuit that detects the start bit from serial input signals. When detecting
the start bit, this circuit writes the data in the serial input data registers 0 to 3 (SIDR0 to SIDR3) with
shifting based on specified transfer rates. The receive parity counter calculates parity in received data.
Transmission Control Circuit
The transmission control circuit is configured with the transmission bit counter, transmission start circuit,
and transmission parity counter. The send bit counter counts sending data. Once this counter completes
sending a piece of data based on the specified data length, then a sending interrupt request is generated. The
sending start circuit starts sending operation by writing to the serial output data registers 0 to 3 (SODR0 to
SODR3). The transmit parity counter generates a parity bit for data to be transmitted if the data is parity-
checked.
Receive shift register
This circuit captures the receiving data, shifting bit by bit, that is input from SIN0 to SIN3 pins. On
completion of reception, this circuit transfers the receiving data to the serial input data registers 0 to 3
(SIDR0 to SIDR3).
Transmit shift register
The data that is written to the serial output data registers 0 to 3 (SODR0 to SODR3) is transferred to the
sending shift register, which outputs it to the SOT pin with shifting bit by bit.
Serial mode register 0 to 3 (SMR0 to SMR3)
Specifies selecting operation modes, enabling/disabling output of serial data to the pin, setting to enable/
disable output of the clock to the pin, setting the arbitrary number of 1 bit to 8 bits to be transferred in the
synchronous communication mode, and setting levels of serial clock output (fixed on "L", fixed on "H")
when not operating.
Serial control register 0 to 3 (SCR0 to SCR3)
Specifies setting the presence or the absence of parity, selection of parity, setting stop bit length, setting
data length, selecting frame data format in the mode 1, clearance of flags, and enabling/disabling of sending
and receiving.
Serial Status Register 0 to 3 (SSR0 to SSR3)
Checking sending and receiving, or the states of errors, and specifies enabling/disabling sending and
receiving interrupt requests.
CHAPTER 21 UART
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