Fujitsu F2MC-16LX Hardware Manual page 500

CHAPTER 21 UART
Table 21.4-1 Functional Description of Each Bit in Serial Control Register 0 to 3 (SCR0 to SCR3)
Bit name
PEN:
bit 15
Parity enable bit
P:
bit 14 Parity selection
bit
SBL:
bit 13 Stop bit length
selection bit
CL:
bit 12 Data length
selection bit
AD:
bit 11 Address/Data
selection bit
REC:
bit 10 Receive error flag
clear bit
RXE:
Reception
bit 9
operation enable
bit
TXE:
Transmission
bit 8
operation enable
bit
484
• Specify whether to add (at sending) or detect (at receiving) a parity bit.
Note: In operation mode1 and operation mode 2, parity bit cannot be appended. Always set
this bit to "0".
• Select either odd or even parity when the use of the parity bit has been selected (SCR0 to
SCR3: PEN = 1).
• Set the length of the stop bits (transmit data's frame end mark) in operation mode 0 and
operation mode 1 (asynchronous).
Note: During receiving data, only the first bit of the stop bit is detected in all cases.
• Specify the data length of data to be transmitted and received.
It is only operation mode 0 to be able to select seven bits. In operation mode 1 and
operation mode 2, be sure to set a data length of 8 bits.
• In operation mode 1, set the data format of frames to be transmitted/received.
• When the bit is set to "0": The frame format is set to data frame.
• When the bit is set to "1": The frame format is set to address data frame.
• Clear the reception error flags (SSR0 to SSR3: FRE, ORE, PE) in the serial status register to
"0".
• When the bit is set to "0": The FRE, ORE, and PE flags are cleared.
• When the bit is set to "1": No effect.
• When read: "1" is always read.
Note: When the receiving interrupt is set to be enabled (SSR0 to SSR3:RIE=1), REC bit
may be set to "0" as long as each of FRE, ORE, PE flag is set to "1".
• The bit enables or disables the UART for reception.
• When the bit is set to "0": Reception is disabled.
• When the bit is set to "1": Reception is enabled.
Note: During receiving data, if the receiving operation is set to be disabled, the receiving
operation is halted after in-coming data is stored in the serial input data register.
• The bit enables or disables the UART for transmission.
• When the bit is set to "0": Transmission is disabled.
• When the bit is set to "1": Transmission is enabled.
Note: If transfer operation is set to be disabled during data transfer, the transfer operation is
stopped on completion of data transfer of the serial output data register.
Functions