Output Compare - Fujitsu F2MC-16LX Hardware Manual

12.2.2

Output Compare

The output compare consists of 16-bit compare registers, compare output pin part, and
a control register. It can reverse the output level for the pin and, at the same time,
generate an interrupt when the 16-bit free-run timer value matches a value set in the 16-
bit compare registers.
• It has a total of four compare registers that can operate independently.
In addition, the output can be set to be controlled by using two compare registers.
• Interrupt can be set through compare-match operation.
List of Output Compare Registers
Figure 12.2-9 lists the output compare registers.
ch0:007919
H
C15
ch1:00791B
H
R/W R/W
ch2:00791D
H
ch3:00791F
H
ch0:007918
H
C07
ch1:00791A
H
R/W R/W
ch2:00791C
H
ch3:00791E
H
ch1:000055
H
ch3:000057
H
ch0:000054
H
ICP1 ICP0 ICE1 ICE0
ch2:000056
H
R/W R/W
Note:
If you rewrite compare registers, you must rewrite them in a compare interrupt routine or in the state
of disabled compare operation to ensure that compare-match operation and write operation never
occur at the same time.
Figure 12.2-9 List of Output Compare Registers
15 14 13 12
C14 C13 C12
R/W R/W R/W
7 6 5 4
C06 C05 C04
R/W R/W R/W
15 14 13 12
CMOD OTE1 OTE0 OTD1 OTD0
- - -
R/W R/W
7 6 5 4
R/W R/W
11 10 9 8
C11 C10 C09 C08
R/W R/W R/W
3 2 1 0
C03 C02 C01 C00
R/W R/W R/W
11 10 9 8
R/W R/W R/W
3 2 1 0
CST1 CST0
- -
R/W R/W
CHAPTER 12 16-BIT I/O TIMER
OCCP0 to OCCP3
Output compare register upper
XXXXXXXX
Initial value
B
OCCP0 to OCCP3
Output compare register lower
Initial value
XXXXXXXX
B
OCS1/OCS3
Output compare
control register upper
Initial value ---00000
B
OCS0/OCS2
Output compare
control register lower
Initial value 0000--00
B
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