Ep0 Control Register (Ep0C) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 13 USB FUNCTION
13.3.2

EP0 Control Register (EP0C)

EP0 control register (EP0C) controls concerning end point 0.
EP0 Control Register (EP0C)
Figure 13.3-4 shows the bit configuration of the EP0 control register (EP0C).
Address bit 7
0000D2 Reserved
H
0
R/W
Address bit 15
0000D3 Reserved
H
Note:
Ensure that you must set the EP0 control register (EP0C), except bit 9 STAL, when both bit 7 RST of
the UDC control register (UDCC) and bit 7 BFINI of the EP0I/EP0O status register (EP0IS/EP0OS)
are 1 and must not rewrite it while the USB is operating.
The following describes the function of each bit in the EP0 control register (EP0C).
[bit 15 to bit 12] Reserved bit
This bit is reserved bit. Writing has no effect on the operation. Reading is indeterminate.
[bit 11, bit 10] Reserved bit
It is reserved bit. Please write "0".
The bit always reads "0" when read.
[bit 9] STAL:STALL EndPoint0 set bit
Setting the STAL bit can put EndPoint0 in STALL status (STALL response).
STAL
0
1
Note:
The STALL response is continued to the host while the STAL bit is set. The USB Function returns
from STALL status when it receives a normal SETUP packet after the STAL bit is deselected.
274
Figure 13.3-4 EP0 Control Register (EP0C)
6 5 4
1 0 0
14 13 12
Reserved Reserved Reserved
Release of state of STALL
Set of state of STALL (STALL response)
3 2 1
PKS0
0 0 0
R/W
11 10 9
Reserved Reserved STAL
0 0 0
R/W R/W R/W
Operating mode
0
EP0 control register
←
0
Initial value
←
Access
8
Reserved
←
0
Initial value
←
R/W
Access